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1. general description the hef4049b provides six inverting buffers with high current output capability suitable for driving ttl or high capaci tive loads. since input voltages in excess of the buffers? supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 v to standard ttl levels. their guaranteed fan-out into common bipolar logic elements is shown in table 3 . it operates over a recommended v dd power supply range of 3 v to 15 v referenced to v ss (usually ground). unused inputs must be connected to v dd , v ss , or another input. it is also suitable for use over the industrial ( ? 40 c to +85 c) temperature range. 2. features ? accepts input voltages in excess of the supply voltage ? fully static operation ? 5 v, 10 v, and 15 v parametric ratings ? standardized symmetrical output characteristics ? operates across the full industrial temperature range ? 40 c to +85 c ? complies with jedec standard jesd 13-b 3. applications ? industrial ? locmos (local oxidation cmos) to dtl/ttl converter ? high sink current for driving two ttl loads ? high-to-low level logic conversion 4. ordering information hef4049b hex inverting buffers rev. 08 ? 2 december 2009 product data sheet table 1. ordering information all types operate from ? 40 c to +85 c. type number package name description version HEF4049BP dip16 plastic dual in-line pa ckage; 16 leads (300 mil) sot38-4 hef4049bt so16 plastic small outline packa ge; 16 leads; body width 3.9 mm sot109-1
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 2 of 11 nxp semiconductors hef4049b hex inverting buffers 5. functional diagram 6. pinning information 6.1 pinning 6.2 pin description fig 1. logic symbol fig 2. logic diagram for one gate fig 3. input protection circuit 001aai33 1 3 1a 1y 2 5 2a 2y 4 7 3a 3y 6 9 4a 4y 10 11 5a 5y 12 14 6a 6y 15 mna34 1 a y 001aae60 4 input v ss fig 4. pin configuration hef4049b v dd n.c. 1y 6y 1a 6a 2y n.c. 2a 5y 3y 5a 3a 4y v ss 4a 001aae602 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description v dd 1 supply voltage 1y to 6y 2, 4, 6, 10, 12, 15 output
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 3 of 11 nxp semiconductors hef4049b hex inverting buffers 7. functional description 8. limiting values [1] for dip16 package: p tot derates linearly with 12 mw/k above 70 c. [2] for so16 package: p tot derates linearly wi th 8 mw/k above 70 c. 9. recommended operating conditions 1a to 6a 3, 5, 7, 9, 11, 14 input v ss 8 ground supply voltage n.c. 13, 16 not connected table 2. pin description ?continued symbol pin description table 3. guaranteed fan-out driven element guaranteed fan-out standard ttl 2 74 ls 9 74 l 16 table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +18 v i ik input clamping current v i < ? 0.5 v or v i >v dd + 0.5 v - 10 ma v i input voltage ? 0.5 v dd + 0.5 v i ok output clamping current v o < ? 0.5 v or v o >v dd + 0.5 v - 10 ma i i/o input/output current - 10 ma i dd supply current - 50 ma t stg storage temperature ? 65 +150 c t amb ambient temperature ? 40 +85 c p tot total power dissipation t amb ? 40 c to +85 c dip16 package [1] -750mw so16 package [2] -500mw p power dissipation per output - 100 mw table 5. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3 - 15 v v i input voltage 0 - v dd v t amb ambient temperature in free air ? 40 - +85 c
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 4 of 11 nxp semiconductors hef4049b hex inverting buffers 10. static characteristics t/ v input transition rise and fall rate v dd = 5 v - - 3.75 s/v v dd = 10 v - - 0.5 s/v v dd = 15 v - - 0.08 s/v table 5. recommended operating conditions ?continued symbol parameter conditions min typ max unit table 6. static characteristics v ss = 0 v; v i = v ss or v dd unless otherwise specified. symbol parameter conditions v dd t amb = ? 40 c t amb = 25 c t amb = 85 c unit min max min max min max v ih high-level input voltage | i o | < 1 a 5 v 3.5 - 3.5 - 3.5 - v 10 v 7.0 - 7.0 - 7.0 - v 15 v 11.0 - 11.0 - 11.0 - v v il low-level input voltage | i o | < 1 a 5 v - 1.5 - 1.5 - 1.5 v 10 v - 3.0 - 3.0 - 3.0 v 15 v - 4.0 - 4.0 - 4.0 v v oh high-level output voltage | i o | < 1 a 5 v 4.95 - 4.95 - 4.95 - v 10 v 9.95 - 9.95 - 9.95 - v 15 v 14.95 - 14.95 - 14.95 - v v ol low-level output voltage | i o | < 1 a 5 v - 0.05 - 0.05 - 0.05 v 10 v - 0.05 - 0.05 - 0.05 v 15 v - 0.05 - 0.05 - 0.05 v i oh high-level output current v o = 2.5 v 5 v ? 1.7 - ? 1.4 - ? 1.1 - ma v o = 4.6 v 5 v ? 0.52 - ? 0.44 - ? 0.36 - ma v o = 9.5 v 10 v ? 1.3 - ? 1.1 - ? 0.9 - ma v o = 13.5 v 15 v ? 3.6 - ? 3.0 - ? 2.4 - ma i ol low-level output current v o = 0.4 v 4.75 v 3.5 - 2.9 - 2.3 - ma v o = 0.5 v 10 v 12.0 - 10.0 - 8.0 - ma v o = 1.5 v 15 v 24.0 - 20.0 - 16.0 - ma i i input leakage current v dd = 15 v 15 v - 0.3 - 0.3 - 1.0 a i dd supply current i o = 0 a 5 v - 4.0 - 4.0 - 30 a 10 v - 8.0 - 8.0 - 60 a 15 v - 16.0 - 16.0 - 120 a c i input capacitance - - - 7.5 - - pf
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 5 of 11 nxp semiconductors hef4049b hex inverting buffers 11. dynamic characteristics [1] the typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (c l in pf). table 7. dynamic characteristics v ss = 0 v; c l = 50 pf; t r = t f 20 ns; t amb = 25 c; unless otherwise specified. symbol parameter conditions v dd extrapolation formula min typ max unit t phl high to low propagation delay na to ny; see figure 5 5 v [1] 26 ns + (0.18 ns/pf)c l -3570ns 10 v 11 ns + (0.08 ns/pf)c l -1530ns 15 v 9 ns + (0.05 ns/pf)c l -1225ns t plh low to high propagation delay na to ny; see figure 5 5 v [1] 23 ns + (0.55 ns/pf)c l - 50 100 ns 10 v 14 ns + (0.23 ns/pf)c l -2550ns 15 v 12 ns + (0.16 ns/pf)c l -2040ns t thl high to low output transition time see figure 5 5 v [1] 3 ns + (0.35 ns/pf)c l -2040ns 10 v 3 ns + (0.14 ns/pf)c l -1020ns 15 v 2 ns + (0.09 ns/pf)c l - 7 14 ns t tlh low to high output transition time see figure 5 5 v [1] 10 ns + (1.00 ns/pf)c l - 60 120 ns 10 v 9 ns + (0.42 ns/pf)c l -3060ns 15 v 6 ns + (0.28 ns/pf)c l -2040ns table 8. dynamic power dissipation p d p d can be calculated from the formulas shown. v ss = 0 v; t r = t f 20 ns; t amb = 25 c. symbol parameter v dd typical formula for p d ( w) where: p d dynamic power dissipation 5 v p d = 2500 f i + (f o c l ) v dd 2 f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v dd = supply voltage in v; (f o c l ) = sum of the outputs. 10 v p d = 11000 f i + (f o c l ) v dd 2 15 v p d = 35000 f i + (f o c l ) v dd 2
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 6 of 11 nxp semiconductors hef4049b hex inverting buffers 12. waveforms measurement points are given in table 9 . v ol and v oh are typical output voltage levels that occur with the output load. fig 5. input (na) to output (ny) propagation delays and transition times 001aai33 6 input output t plh t phl 0 v v i v m v m v oh v ol t tlh t thl 90 % 10 % 10 % 90 % t r t f table 9. measurement points input output v m v i v m v x v y 0.5v dd 0 v to v dd 0.5v dd 0.1v dd 0.9v dd test data is given in table 10 . definitions for test circuit: c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. fig 6. load circuitry for switching times v dd v i v o 001aag18 2 dut c l r t g table 10. test data supply voltage input load v i v m t r , t f c l 5vto15v v dd 0.5v i 20 ns 50 pf
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 7 of 11 nxp semiconductors hef4049b hex inverting buffers 13. package outline fig 7. package outline sot38-4 (dip16) references outline version european projection issue date iec jedec jeita sot38-4 95-01-14 03-02-13 m h c (e ) 1 m e a l seating plane a 1 w m b 1 b 2 e d a 2 z 16 1 9 8 e pin 1 index b 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 0.76 4.2 0.51 3.2 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.03 0.17 0.02 0.13 d ip16: plastic dual in-line package; 16 leads (300 mil) sot38 -4
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 8 of 11 nxp semiconductors hef4049b hex inverting buffers fig 8. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale s o16: plastic small outline package; 16 leads; body width 3.9 mm sot109 -1
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 9 of 11 nxp semiconductors hef4049b hex inverting buffers 14. abbreviations 15. revision history table 11. abbreviations acronym description dtl diode transistor logic locmos local oxidation cmos ttl transistor transistor logic table 12. revision history document id release date data sheet status change notice supersedes hef4049b_8 20091202 product data sheet - hef4049b_7 modifications: ? section 8 ? limiting values ? t/ v values updated. hef4049b_7 20090721 product data sheet - hef4049b_6 hef4049b_6 20090325 product data sheet - hef4049b_5 hef4049b_5 20081111 product data sheet - hef4049b_4 hef4049b_4 20080704 product data sheet - hef4049b_cnv_3 hef4049b_cnv_3 19950101 product specification - hef4049b_cnv_2 hef4049b_cnv_2 19950101 pr oduct specification - -
hef4049b_8 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 08 ? 2 december 2009 10 of 11 nxp semiconductors hef4049b hex inverting buffers 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
nxp semiconductors hef4049b hex inverting buffers ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 2 december 2009 document identifier: hef4049b_8 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 functional description . . . . . . . . . . . . . . . . . . . 3 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 recommended operating conditions. . . . . . . . 3 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 4 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 10 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 17 contact information. . . . . . . . . . . . . . . . . . . . . 10 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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